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Espressif · current

ESP32-DevKitC

Small Espressif development board with an ESP32-WROOM/WROVER module, USB-to-UART bridge and breadboard-friendly headers.

Evidence: Inferred 2 sources · latest retrieved 2026-10-18 · audited

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Key specs

Logic level
3.3 V Evidence: Documented
CPU clock max
240 MHz Evidence: Documented
SRAM
520 KB Evidence: Documented
Operating voltage
3.3 V Evidence: Documented
Module options
ESP32-WROOM-32E, WROOM-32UE, WROVER-E, WROVER-IE Evidence: Documented
Flash options
4 MB (WROOM-32E/32UE variants in the guide) / 8 MB (WROVER-E/IE variants in the guide) Evidence: Documented

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Comparisons

Read the caveats

Suggested for: Log temperature over Wi-Fi, Compare boards: documented capabilities

All specifications 11
SpecValueEvidence
Module optionsESP32-WROOM-32E, WROOM-32UE, WROVER-E, WROVER-IEEvidence: Documented
Flash options4 MB (WROOM-32E/32UE variants in the guide) / 8 MB (WROVER-E/IE variants in the guide)Evidence: Documented
PSRAM options8 MB (WROVER-E/IE variants in the guide); none on the WROOM variants in the guideEvidence: Documented
USB uart bridge max rate3 MbpsEvidence: Documented
USB connectorMicro-USBEvidence: Documented
Power optionsUSB 5V, 5V header pin, or 3V3 header pin (mutually exclusive)Evidence: Documented
Header pins per side19
J2 and J3 each list 19 pins
Evidence: Documented
Programmable functionsPWM, ADC, DAC, I2C, I2S, SPIEvidence: Documented
CPU clock max240 MHz
ESP32 chip: max CPU frequency 240 MHz (160 MHz for the NRND ESP32-S0WD only); chip-level, not board-specific
Evidence: Documented
SRAM520 KB
Chip-level 520 KB SRAM (plus 16 KB RTC SRAM, 448 KB ROM); excludes external PSRAM
Evidence: Documented
Operating voltage3.3 V
Chip supply (VDDA/VDD3P3/VDD3P3_RTC) 2.3-3.6 V, typ 3.3 V; min 3.0 V for chips with in-package 3.3 V flash/PSRAM. Chip-level recommended supply, not a board GPIO-level statement
Evidence: Documented
Caveats

logic_level_v=3.3 is class 1 per the ESP32-WROOM-32E datasheet (3.0-3.6 V supply; VIH/VIL referenced to VDD); the board guide itself only shows a 3V3 rail (audited 2026-10-18). Variants differ in flash/PSRAM. GPIO16/17 are usable only on WROOM/SOLO-1 variants and reserved on WROVER variants (guide footnote [3]). Guide note on C15: on earlier V4 boards C15 may cause boot into Download mode / affect clock output on GPIO0. status 'current' reflects that the guide shows no EOL marker; no separate EOL/NRND notice was checked; an older V2 exists. Avoid GPIO6-11 (flash). (2026-10-18) cpu_clock_max, sram, operating_voltage come from the ESP32 chip datasheet v5.3 (chip-level); the datasheet does not map which chip variant is inside each WROOM/WROVER module, so values assume the standard 240 MHz dual-core variants (the guide does not list an ESP32-S0WD module). The WROOM-32E module datasheet was read by the Auditor for the logic-level claim. operating_voltage is the chip supply range; the GPIO logic level is covered by clm-esp32dk-004 (class 1). Flash/PSRAM (2026-10-18): the specs list only the variants named in the DevKitC guide. Module datasheets cover a wider range: ESP32-WROOM-32E 4/8/16 MB flash and none or 2 MB PSRAM; ESP32-WROVER-E 4/8/16 MB flash and 8 MB PSRAM (an EOL 2 MB PSRAM variant exists).

Claims 4
  • ESP32-DevKitC is a small ESP32-based dev board by Espressif with most I/O pins broken out to headers, usable on a breadboard. Evidence: Documented

    Source: src-esp32-devkitc-guide

  • Power must come from exactly one of Micro USB, 5V pin, or 3V3 pin, otherwise board/supply can be damaged. Evidence: Documented

    Source: src-esp32-devkitc-guide

  • GPIO6-11 (CLK, D0-D3, CMD) are used for SPI flash and should be avoided. Evidence: Documented

    Source: src-esp32-devkitc-guide

  • GPIO logic level is 3.3 V. Evidence: Documented

    Source: src-esp32-devkitc-guide

Sources 2

How we verify